On-chip infrastructure to leverage system reliability for space applications

by Fabian Luis Vargas (Presenter)
IHP – Microelectronics, Germany

Abstract – Technology scaling, which made electronics accessible and affordable for almost everyone on the globe, has advanced integrated circuit (IC) and electronics since the sixties. Nevertheless, it is well recognized that such scaling has introduced new (and major) reliability challenges to the semiconductor industry.This talk summarizes the on-chip infrastructure such as sensors and dedicated HW redundancy under development at IHP Microelectronics. This infrastructure deals with, for instance, detecting single-event upset (SEU) in memory elements and single-event transient (SET) in logic, measuring electronics aging and tracking in-field real-time circuit speed performance degradation during IC lifetime. Ultimately, this infrastructure allows predicting in-flight SEU rate and remaining IC life-span. Dedicated on-chip watchdogs to guarantee mixed-criticality task execution in real-time operating system (RTOS) is further introduced. Embedded systems based on such watchdogs are assumed to be compliant with the ARINC 653 Std.Currently, this on-chip infrastructure is being implemented by IHP in different versions of a RISC-V processor. Such design is based on a CMOS 130nm rad-hard technology also developed at IHP. An FPGA-mapped demonstrator of one of the developed RISC-V processors and experimental results will be briefly presented.

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