{"id":196,"date":"2024-07-08T07:48:54","date_gmt":"2024-07-08T07:48:54","guid":{"rendered":"http:\/\/asaclab.polito.it\/fpl2024\/?page_id=196"},"modified":"2024-08-28T09:43:32","modified_gmt":"2024-08-28T09:43:32","slug":"program-2","status":"publish","type":"page","link":"http:\/\/asaclab.polito.it\/fpl2024\/program-2\/","title":{"rendered":"Program"},"content":{"rendered":"\n<figure class=\"wp-block-image aligncenter size-large is-resized\"><img decoding=\"async\" src=\"http:\/\/asaclab.polito.it\/seressa23\/wp-content\/uploads\/sites\/2\/2023\/09\/banner_registration-e1695384325302-1024x119.png\" alt=\"\" class=\"wp-image-40\" style=\"width:1206px;height:140px\"\/><\/figure>\n\n\n\n<p><\/p>\n\n\n\n<h1 class=\"wp-block-heading has-text-align-center\">Program<\/h1>\n\n\n\n<p><\/p>\n\n\n\n<html><head><style>\ntable { width: 100%; border-collapse: collapse; }\nth, td { border: 1px solid black; padding: 8px; text-align: left; }\ntr:nth-child(even) { background-color: #f2f2f2; }\nth { background-color: #4CAF50; color: white; }\ntd.time { width: 150px; }\ntd.session { width: 250px; }\ntd.details { width: 600px; }\n<\/style><\/head><body>\n\n\n<div >\n        <div class=\" plethoraplugins-tabs-container plethoraplugins-tabs-container--horizontal plethoraplugins-theme__minimal plethoraplugins-theme__basic \" \n\t\t\tdata-pds-tabs--layout=\"horizontal\"  \n\t\t\tdata-pds-tabs--theme=\"basic\"  \n\t\t\tdata-pds-tabs--mobile-breakpoint-forced=\"\"\n\t\t\t data-pds-tabs--responsive=\"accordion\" \n\t\t\t\t\t data-pds-tabs--responsive-accordion-collapsed-initially=\"false\" data-pds-tabs--accordion-icon-type=\"\" data-pds-tabs--accordion-icon=\"true\"  data-pds-tabs--accordion-icon-size=\"\"  data-pds-tabs--accordion-heading-level=\"h3\" data-pds-tabs--accordion-auto-close=\"true\" >\n            <div class=\"plethoraplugins-tabs\"  >\n              <ul><li>\n                        <a \n                                href=\"#2nd_september\"\n                                class=\" active\" \n                            >\n                            <span>2nd September <\/span>\n                        <\/a>\n                    <\/li><li>\n                        <a \n                                href=\"#3rd_september\"\n                                class=\"\" \n                            >\n                            <span>3rd September <\/span>\n                        <\/a>\n                    <\/li><li>\n                        <a \n                                href=\"#4th_september\"\n                                class=\"\" \n                            >\n                            <span>4th September <\/span>\n                        <\/a>\n                    <\/li><li>\n                        <a \n                                href=\"#5th_september\"\n                                class=\"\" \n                            >\n                            <span>5th September<\/span>\n                        <\/a>\n                    <\/li><li>\n                        <a \n                                href=\"#6th_september\"\n                                class=\"\" \n                            >\n                            <span>6th September<\/span>\n                        <\/a>\n                    <\/li><\/ul>\n            <\/div>\n            <div class=\"plethoraplugins-tabs--content\" >\n                \n<div class=\"\"  data-pds-tabs--accordion-initially-open=\"false\" >\n\n<h2>2nd September<\/h2>\n<table>\n<tbody><tr><th class=\"time\">TIME<\/th><th class=\"session\">SESSION<\/th><th class=\"details\" colspan=\"2\">DETAILS<\/th><\/tr>\n<tr><td rowspan=\"1\" class=\"time\">10:30 &#8211; 12:30<\/td><td rowspan=\"1\" class=\"session\"><b>Registration<\/b> <\/td><tr><td rowspan=\"1\" class=\"time\">12:30 &#8211; 13:30<\/td><td rowspan=\"1\" class=\"session\"><b>Lunch<\/b> <\/td><td rowspan=\"1\" colspan=\"2\" class=\"details\"><\/td><\/tr><tr><td rowspan=\"7\" class=\"time\">13:30 &#8211; 17:00<\/td><td rowspan=\"7\" class=\"session\"><b>TUTORIAL: Designing for the Neural Processing Unit on AMD Ryzen AI with Open-Source Tools<\/b><br><small>Chair: Dr. Mario Ruiz<\/small> <\/td><td rowspan=\"1\" class=\"time\">13:30 &#8211; 14:00<\/td><td rowspan=\"1\" class=\"details\"><b>Tutorial Welcome and General Introductions<\/b><br><small>Dr. Mario Ruiz<\/small><\/td><\/tr><tr><td rowspan=\"1\" class=\"time\">14:00 &#8211; 14:30<\/td><td rowspan=\"1\" class=\"details\"><b>Introduction to Ryzen AI NPU and Riallto<\/b><br><small>Dr. Mario Ruiz<\/small><\/td><\/tr><tr><td rowspan=\"1\" class=\"time\">14:30 &#8211; 15:00<\/td><td rowspan=\"1\" class=\"details\"><b>Explore NPU architectural features with Riallto<\/b><br><small>Dr. Mario Ruiz<\/small><\/td><\/tr><tr><td rowspan=\"1\" class=\"time\">15:00 &#8211; 15:30<\/td><td rowspan=\"1\" class=\"details\"><b>Coffee Break<\/b><br><small><\/small><\/td><\/tr><tr><td rowspan=\"1\" class=\"time\">15:30 &#8211; 16:00<\/td><td rowspan=\"1\" class=\"details\"><b>Write your own compute kernel and connectivity<\/b><br><small>Dr. Mario Ruiz<\/small><\/td><\/tr><tr><td rowspan=\"1\" class=\"time\">16:00 &#8211; 16:30<\/td><td rowspan=\"1\" class=\"details\"><b>IRON AIE<\/b><br><small>Dr. Mario Ruiz<\/small><\/td><\/tr><tr><td rowspan=\"1\" class=\"time\">16:30 &#8211; 17:00<\/td><td rowspan=\"1\" class=\"details\"><b>AMD Ryzen AI Software<\/b><br><small>Dr. Mario Ruiz<\/small><\/td><\/tr><\/tbody><\/table>\n<p>We regret to inform you that the Workshop on Security for Custom Computing Machines (SCCM) has been postponed to avoid overlap with Conference on Cryptographic Hardware and Embedded Systems (CHES) and will not be held during FPL 2024<\/p>\n\n<\/div>\n\n<div class=\"\"  data-pds-tabs--accordion-initially-open=\"false\" >\n\n<p><span style=\"margin: 0px; padding: 0px;\"><strong>IMPORTANT:<\/strong>To attend <\/span>AMD&#8217;s Tutorial on &#8220;<strong>Co-Designing Compute Architectures That Can Accelerate Neural Networks Using FINN,&#8221;<\/strong> it is mandatory to register at the following link to access AWS instances to use during the tutorial.&nbsp; LINK:&nbsp;<a href=\"https:\/\/account.amd.com\/en\/forms\/contact-forms\/amd-research-finn-tutorial24-registration-en.html\">https:\/\/account.amd.com\/en\/forms\/contact-forms\/amd-research-finn-tutorial24-registration-en.html<\/a><\/p>\n\n\n\n<h2>3rd September<\/h2>\n<table>\n  <tbody>\n    <tr>\n      <th class=\"time\">TIME<\/th>\n      <th class=\"session\">SESSION<\/th>\n      <th class=\"details\" colspan=\"2\">DETAILS<\/th>\n    <\/tr>\n    <tr>\n      <td rowspan=\"1\" class=\"time\">08:00 &#8211; 08:30<\/td>\n      <td rowspan=\"1\" class=\"session\">\n        <b>Registration<\/b>\n      <\/td>\n      <td rowspan=\"1\" colspan=\"2\" class=\"details\"><\/td>\n    <\/tr>\n    <tr>\n      <td rowspan=\"4\" class=\"time\">08:30 &#8211; 12:30<\/td>\n      <td rowspan=\"1\" class=\"session\">\n        <b>TUTORIAL: SODA Synthesizer <\/b>\n        <br>\n        <small>Chair: Antonino Tumeo<\/small>\n      <\/td>\n      <td rowspan=\"1\" colspan=\"2\" class=\"details\">\n        <a href=\"https:\/\/hpc.pnl.gov\/SODA\/tutorials\/2024\/FPL24.html\">Additional Info<\/a>\n      <\/td>\n    <\/tr>\n    <tr>\n      <td rowspan=\"3\" class=\"session\">\n        <b> TUTORIAL: Co-Designing Compute Architectures That Can Accelerate Neural Networks Using FINN (Part I)<\/b>\n        <br>\n        <small>Chair: Thomas Preu\u00dfer, Jakoba Petri-Koenig, Felix Jentzsch, Lukas Stasytis, Michaela Blott and Zaid Al-Ars<\/small>\n      <\/td>\n      <td rowspan=\"1\" class=\"time\">08:30 &#8211; 10:30<\/td>\n      <td rowspan=\"1\" class=\"details\">\n        <b>General introduction to FINN<\/b>\n        <br>In this tutorial, we present FINN, an open-source experimental framework by AMD Research to help the broader community explore QNN inference on FPGAs. FINN builds high-performance dataflow-style FPGA architectures specific to the custom network while providing a full-stack solution from quantization-aware model training to bitfile generation.\n      <\/td>\n    <\/tr>\n    <tr>\n      <td rowspan=\"1\" class=\"time\">10:30 &#8211; 11:00<\/td>\n      <td rowspan=\"1\" class=\"details\">\n        <b>Coffee Break<\/b>\n        <br>\n        <small><\/small>\n      <\/td>\n    <\/tr>\n    <tr>\n      <td rowspan=\"1\" class=\"time\">11:00 &#8211; 12:30<\/td>\n      <td rowspan=\"1\" class=\"details\">\n        <b>FINN community and Poster Session<\/b>\n        <br>\n      <\/td>\n    <\/tr>\n    <tr>\n      <td rowspan=\"1\" class=\"time\">12:30 &#8211; 13:30<\/td>\n      <td rowspan=\"1\" class=\"session\">\n        <b>Lunch<\/b>\n      <\/td>\n      <td rowspan=\"1\" colspan=\"2\" class=\"details\"><\/td>\n    <\/tr>\n    <tr>\n      <td rowspan=\"1\" class=\"time\">13:30 &#8211; 17:15<\/td>\n      <td rowspan=\"1\" class=\"session\">\n        <b>TUTORIAL: Co-Designing Compute Architectures That Can Accelerate Neural Networks Using FINN (Part II) <\/b>\n        <br>\n        <small>Chair: Thomas Preu\u00dfer, Jakoba Petri-Koenig, Felix Jentzsch, Lukas Stasytis, Michaela Blott and Zaid Al-Ars<\/small>\n      <\/td>\n      <td rowspan=\"1\" class=\"time\">13:30 &#8211; 17:15<\/td>\n      <td rowspan=\"1\" class=\"details\">\n        <b>Hands-on<\/b>\n        <br>\n        <b>Beginners<\/b>\n        <br>\n        <ul>\n          <li>Training a quantized MLP on the UNSW-NB15 dataset with Brevitas <\/li>\n          <li>Exporting the trained network to FINN-ONNX + verifying in FINN compiler<\/li>\n          <li>Performance estimation and bitfile generation with the FINN compiler <\/li>\n        <\/ul>\n        <b>Advanced<\/b>\n        <br>\n        <ul>\n          <li>Using a simple CNV to explore the various options to configure the FINN builder tool<\/li>\n        <\/ul>\n      <\/td>\n    <\/tr>\n    <tr>\n        <\/tr>\n    <tr>\n      <td rowspan=\"1\" class=\"time\">17:00 &#8211; 19:00<\/td>\n      <td rowspan=\"1\" class=\"session\">\n        <b>Welcome Reception <\/b>\n      <\/td>\n      <td rowspan=\"1\" colspan=\"2\" class=\"details\">   <b> <a href=\"http:\/\/asaclab.polito.it\/fpl2024\/soacial-activity\/#welcome_reception\">Welcome Reception Info <\/a> <\/b> <\/td>\n    <\/tr>\n  <\/tbody>\n<\/table>\n\n<\/div>\n\n<div class=\"\"  data-pds-tabs--accordion-initially-open=\"false\" >\n\n<html><head><style>\ntable { width: 100%; border-collapse: collapse; }\nth, td { border: 1px solid black; padding: 8px; text-align: left; }\ntr:nth-child(even) { background-color: #f2f2f2; }\nth { background-color: #4CAF50; color: white; }\ntd.time { width: 150px; }\ntd.session { width: 250px; }\ntd.details { width: 600px; }\n<\/style><\/head><body>\n    <h2>4th September<\/h2>\n<table>\n  <tr>\n    <th class='time'>TIME<\/th>\n    <th class='session'>SESSION<\/th>\n    <th class='details' colspan=2>DETAILS<\/th>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>08:00 &#8211; 08:30<\/td>\n    <td rowspan='1' class='session'>\n      <b>Registration<\/b>\n    <\/td>\n    <td rowspan='1' colspan='2' class='details'><\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>08:30 &#8211; 08:40<\/td>\n    <td rowspan='1' class='session'>\n      <b>Opening<\/b>\n    <\/td>\n    <td rowspan='1' colspan='2' class='details'><\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>08:40 &#8211; 09:40<\/td>\n    <td rowspan='1' class='session'>\n      <b>Keynote<\/b>\n      <br>\n      <small>Chair: Luciano Lavagno<\/small>\n    <\/td>\n    <td rowspan='1' class='time'>08:40 &#8211; 09:40<\/td>\n    <td rowspan='1' class='details'>\n      <b><a href=\"http:\/\/asaclab.polito.it\/fpl2024\/keynotes\/#keynote_1\">AMD Vitis\u2122 High-Level Synthesis (HLS) Tool: Principles and Evolution<\/a><\/b>\n      <br>\n      <small>Alain Darte<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='3' class='time'>09:40 &#8211; 10:30<\/td>\n    <td rowspan='3' class='session'>\n      <b>Session: Applications<\/b>\n      <br>\n      <small>Chair: Carsten Trinitis<\/small>\n    <\/td>\n    <td rowspan='1' class='time'>09:40 &#8211; 10:00<\/td>\n    <td rowspan='1' class='details'>\n      <b>Exploring the Versal AI Engines for Signal Processing in Radio Astronomy<\/b>\n      <br>\n      <small>Victor van Wijhe, Vincent Sprave, Daniele Passaretti, Nikolaos Alachiotis, Gerrit Grutzeck, Thilo Pionteck and Steven van der Vlugt<\/small>\n    <\/td>\n  <tr>\n    <td rowspan='1' class='time'>10:00 &#8211; 10:20<\/td>\n    <td rowspan='1' class='details'>\n      <b>JSON-CooP: A JSON Decompression\/Parsing Co-Design for FPGAs<\/b>\n      <br>\n      <small>Tobias Hahn, Stefan Wildermann and J\u00fcrgen Teich<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>10:20 &#8211; 10:30<\/td>\n    <td rowspan='1' class='details'>\n      <b>KIT: Kernel Isotropic Transformation of Bilateral Filters for Image Denoising on FPGA<\/b>\n      <br>\n      <small>Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci and Stefania Perri<\/small>\n    <\/td>\n\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>10:30 &#8211; 11:00<\/td>\n    <td rowspan='1' class='session'>\n      <b>Coffee Break<\/b>\n    <\/td>\n    <td rowspan='1' colspan='2' class='details'><\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='4' class='time'>11:00 &#8211; 12:20<\/td>\n    <td rowspan='4' class='session'>\n      <b>Session: Placement &#038; Routing<\/b>\n      <br>\n      <small>Chair: Dirk Strootbandt<\/small>\n    <\/td>\n    <td rowspan='1' class='time'>11:00 &#8211; 11:20<\/td>\n    <td rowspan='1' class='details'>\n      <b>DynaRapid: Fast-Tracking from C to Routed Circuits (*)<\/b>\n      <br>\n      <small>Andrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipovic and Paolo Ienne<\/small>\n    <\/td>\n  <tr>\n    <td rowspan='1' class='time'>11:20 &#8211; 11:40<\/td>\n    <td rowspan='1' class='details'>\n      <b>The Road Less Traveled: Congestion-Aware NoC Placement and Packet Routing for FPGAs (*)<\/b>\n      <br>\n      <small>Soheil Gholami Shahrouz and Vaughn Betz<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>11:40 &#8211; 12:00<\/td>\n    <td rowspan='1' class='details'>\n      <b>Better Together: Combining Analytical and Annealing Methods for FPGA Placement<\/b>\n      <br>\n      <small>Rachel Selina Rajarathnam, Kate Thurmer, Vaughn Betz, Mahesh A. Iyer and David Z. Pan<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>12:00 &#8211; 12:20<\/td>\n    <td rowspan='1' class='details'>\n      <b>A High-Performance Routing Engine for Large-Scale FPGAs<\/b>\n      <br>\n      <small>Timothy Martin, Dani Maarouf, Shawki Areibi and Gary Grewal<\/small>\n    <\/td>\n  <\/tr>\n\n  <tr>\n    <td rowspan='1' class='time'>12:20 &#8211; 13:20<\/td>\n    <td rowspan='1' class='session'>\n      <b>Lunch<\/b>\n    <\/td>\n    <td rowspan='1' colspan='2' class='details'><\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='5' class='time'>13:20 &#8211; 14:40<\/td>\n    <td rowspan='5' class='session'>\n      <b>Session: High-Bandwidth &#038; Virtual Memory<\/b>\n      <br>\n      <small>Chair: Jeff Goeders<\/small>\n    <\/td>\n    <td rowspan='1' class='time'>13:20 &#8211; 13:40<\/td>\n    <td rowspan='1' class='details'>\n      <b>SERI: High-Throughput Streaming Acceleration of Electron Repulsion Integral Computation in Quantum Chemistry using HBM-based FPGAs (#)<\/b>\n      <br>\n      <small>Philip Stachura, Guanyu Li, Xin Wu, Christian Plessl and Zhenman Fang<\/small>\n    <\/td>\n  <tr>\n    <td rowspan='1' class='time'>13:40 &#8211; 14:00<\/td>\n    <td rowspan='1' class='details'>\n      <b>H2PIPE: High throughput CNN Inference on FPGAs with High-Bandwidth Memory (#)<\/b>\n      <br>\n      <small>Mario Doumet, Marius Stan, Mathew Hall and Vaughn Betz<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>14:00 &#8211; 14:20<\/td>\n    <td rowspan='1' class='details'>\n      <b>FlexiMem: Modular and Reconfigurable Virtual Memory<\/b>\n      <br>\n      <small>Canberk S\u00f6nmez, Mohamed Mahfouz Shahawy, Cemalettin Cem Belentepe and Paolo Ienne<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>14:20 &#8211; 14:30<\/td>\n    <td rowspan='1' class='details'>\n      <b>SoGraph: A State-Aware Architecture for Out-of-Memory Graph Processing on HBM-Equipped FPGAs<\/b>\n      <br>\n      <small>Qianyu Cheng, Zhendong Zheng, Tianhao Jiang, Cheng Tang, Teng Wang, Lei Gong, Xianglan Chen, Chao Wang and Xuehai Zhou<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>14:30 &#8211; 14:40<\/td>\n    <td rowspan='1' class='details'>\n      <b>Leveraging HBM2 for Accelerating k-mer Counting with oneAPI on FPGAs<\/b>\n      <br>\n      <small>Owen Lucas and Alan George<\/small>\n    <\/td>\n  <\/tr>\n\n  <tr>\n    <td rowspan='1' class='time'>14:40 &#8211; 15:10<\/td>\n    <td rowspan='1' class='session'>\n      <b>Coffee Break<\/b>\n    <\/td>\n    <td rowspan='1' colspan='2' class='details'><\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='5' class='time'>15:10 &#8211; 16:20<\/td>\n    <td rowspan='5' class='session'>\n      <b>Session: High-Level Synthesis &#038; Simulation<\/b>\n      <br>\n      <small>Chair: Antonino Tumeo<\/small>\n    <\/td>\n    <td rowspan='1' class='time'>15:10 &#8211; 15:30<\/td>\n    <td rowspan='1' class='details'>\n      <b>StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs (*)<\/b>\n      <br>\n      <small>Jan-Oliver Opdenh\u00f6vel, Christoph Alt, Christian Plessl and Tobias Kenter<\/small>\n    <\/td>\n  <tr>\n    <td rowspan='1' class='time'>15:30 &#8211; 15:50<\/td>\n    <td rowspan='1' class='details'>\n      <b>Efficient Design Space Exploration for Dynamic &#038; Speculative High-Level Synthesis<\/b>\n      <br>\n      <small>Dylan Leothaud, Jean-Michel Gorius, Simon Rokicki and Steven Derrien<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>15:50 &#8211; 16:00<\/td>\n    <td rowspan='1' class='details'>\n      <b>Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits<\/b>\n      <br>\n      <small>Jiantao Liu, Maksymilian Graczyk, Andrea Guerrieri and Lana Josipovi\u0107<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>16:00 &#8211; 16:10<\/td>\n    <td rowspan='1' class='details'>\n      <b>FlexWalker: An Efficient Multi-Objective Design Space Exploration Framework for HLS Design<\/b>\n      <br>\n      <small>Zheyuan Zou, Cheng Tang, Lei Gong, Chao Wang and Xuehai Zhou<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>16:10 &#8211; 16:20<\/td>\n    <td rowspan='1' class='details'>\n      <b>Chimera: A co-simulation framework combining with gem5 and FPGA platform for efficient verification<\/b>\n      <br>\n      <small>Chao Fu, Zengshi Wang and Jun Han<\/small>\n    <\/td>\n  <\/tr>\n   <td rowspan='5' class='time'>16:20 &#8211; 19:00<\/td>\n    <td rowspan='5' class='session'>\n      <b>Exhibition<\/b>\n    <\/td>\n    <td rowspan='1' class='time'>16:20 &#8211; 17:00<\/td>\n    <td rowspan='1' class='details'>\n      <b>Sponsor&#8217;s Talks<\/b>\n    <\/td>\n    <tr>\n    <td rowspan='1' class='time'>17:00 &#8211; 19:00<\/td>\n    <td rowspan='1' class='details'>\n      <b> <a href=\"http:\/\/asaclab.polito.it\/fpl2024\/soacial-activity\/#exhibition_reception\">Exhibition Reception <\/a> <\/b>\n    <\/td>\n  <\/tr>\n \n<\/table>\n\n<\/div>\n\n<div class=\"\"  data-pds-tabs--accordion-initially-open=\"false\" >\n\n<h2>5th September<\/h2>\n<table>\n  <tr>\n    <th class='time'>TIME<\/th>\n    <th class='session'>SESSION<\/th>\n    <th class='details' colspan=2>DETAILS<\/th>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>08:00 &#8211; 08:30<\/td>\n    <td rowspan='1' class='session'>\n      <b>Registration<\/b>\n    <\/td>\n    <td rowspan='1' colspan='2' class='details'><\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>08:30 &#8211; 09:30<\/td>\n    <td rowspan='1' class='session'>\n      <b>Keynote<\/b>\n      <br>\n      <small>Chair: Fabrizio Ferrandi<\/small>\n    <\/td>\n    <td rowspan='1' class='time'>08:30 &#8211; 09:30<\/td>\n    <td rowspan='1' class='details'>\n      <b>\n        <b>\n          <a href=\"http:\/\/asaclab.polito.it\/fpl2024\/keynotes\/#keynote_2\">The Data Center of the Future: Disaggregated, Serverless and Heterogeneous<\/a>\n        <\/b>\n      <\/b>\n      <br>\n      <small>Miriam Leeser<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='3' class='time'>09:30 &#8211; 10:20<\/td>\n    <td rowspan='3' class='session'>\n      <b>Session: Machine Learning 1<\/b>\n      <br>\n      <small>Chair: Thilo Pionteck<\/small>\n    <\/td>\n    <td rowspan='1' class='time'>09:30 &#8211; 09:50<\/td>\n    <td rowspan='1' class='details'>\n      <b>NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions<\/b>\n      <br>\n      <small>Marta Andronic and George A. Constantinides<\/small>\n    <\/td>\n  <tr>\n    <td rowspan='1' class='time'>09:50 &#8211; 10:10<\/td>\n    <td rowspan='1' class='details'>\n      <b>PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs<\/b>\n      <br>\n      <small>Binglei Lou, Richard Rademacher, David Boland and Philip Leong<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>10:10 &#8211; 10:20<\/td>\n    <td rowspan='1' class='details'>\n      <b>Kratos: An FPGA Benchmark for Unrolled Deep Neural Networks with Fine-Grained Sparsity and Mixed Precision<\/b>\n      <br>\n      <small>Xilai Dai, Yuzong Chen and Mohamed Abdelfattah<\/small>\n    <\/td>\n  <\/tr>\n  <\/tr>\n <tr>\n    <td rowspan='1' class='time'>10:20 &#8211; 10:25<\/td>\n    <td rowspan='1' class='session'>\n      <b>Poster Pitches<\/b>\n    <\/td>\n    <td rowspan='1' colspan='2' class='details'><\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>10:25 &#8211; 11:20<\/td>\n    <td rowspan='1' class='session'>\n      <b>Coffee Break and Poster Session<\/b>\n    <\/td>\n    <td rowspan='1' colspan='2' class='details'><\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='3' class='time'>11:20 &#8211; 12:20<\/td>\n    <td rowspan='3' class='session'>\n      <b>Session: Cryptography &#038; Security<\/b>\n      <br>\n      <small>Chair: David Andrews<\/small>\n    <\/td>\n    <td rowspan='1' class='time'>11:20 &#8211; 11:40<\/td>\n    <td rowspan='1' class='details'>\n      <b>UniGuard: A Unified Hardware-oriented Threat Detector for FPGA-based AI Accelerators (#)<\/b>\n      <br>\n      <small>Xiaobei Yan, Han Qiu and Tianwei Zhang<\/small>\n    <\/td>\n  <tr>\n    <td rowspan='1' class='time'>11:40 &#8211; 12:00<\/td>\n    <td rowspan='1' class='details'>\n      <b>A Better Kyber Butterfly for FPGAs<\/b>\n      <br>\n      <small>Jonas Bertels, Quinten Norga and Ingrid Verbauwhede<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>12:00 &#8211; 12:20<\/td>\n    <td rowspan='1' class='details'>\n      <b>Techniques for Exploring Fine-Grained LUT and Routing Aging on a 28nm FPGA<\/b>\n      <br>\n      <small>Hayden Cook and Jeffrey Goeders<\/small>\n    <\/td>\n  <\/tr>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>12:20 &#8211; 13:20<\/td>\n    <td rowspan='1' class='session'>\n      <b>Lunch<\/b>\n    <\/td>\n    <td rowspan='1' colspan='2' class='details'><\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='5' class='time'>13:20 &#8211; 14:40<\/td>\n    <td rowspan='5' class='session'>\n      <b>Session: Architectures<\/b>\n      <br>\n      <small>Chair: Suhaib Fahmy<\/small>\n    <\/td>\n    <td rowspan='1' class='time'>13:20 &#8211; 13:40<\/td>\n    <td rowspan='1' class='details'>\n      <b>A Software-Programmable Neural Processing Unit for Graph Neural Network Inference on FPGAs (#)<\/b>\n      <br>\n      <small>Taikun Zhang, Andrew Boutros, Sergey Gribok, Kwadwo Boateng and Vaughn Betz<\/small>\n    <\/td>\n  <tr>\n    <td rowspan='1' class='time'>13:40 &#8211; 14:00<\/td>\n    <td rowspan='1' class='details'>\n      <b>Revealing Untapped DSP Optimization Potentials for FPGA-Based Systolic Matrix Engines<\/b>\n      <br>\n      <small>Jindong Li, Tenglong Li, Guobin Shen, Dongcheng Zhao, Qian Zhang and Yi Zeng<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>14:00 &#8211; 14:20<\/td>\n    <td rowspan='1' class='details'>\n      <b>SA4: A Comprehensive Analysis and Optimization of Systolic Array Architecture for 4-bit Convolutions<\/b>\n      <br>\n      <small>Geng Yang, Jie Lei, Zhenman Fang, Jiaqing Zhang, Junrong Zhang, Weiying Xie and Yunsong Li<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>14:20 &#8211; 14:30<\/td>\n    <td rowspan='1' class='details'>\n      <b>CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design<\/b>\n      <br>\n      <small>Yiqing Mao, Xuchen Gao, Jiahang Lou, Yunhui Qiu, Wenbo Yin, Wai-Shing Luk and Lingli Wang<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>14:30 &#8211; 14:40<\/td>\n    <td rowspan='1' class='details'>\n      <b>IMAGine: An In-Memory Accelerated GEMV Engine Overlay<\/b>\n      <br>\n      <small>Md Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason Bakos, Miaoqing Huang and David Andrews<\/small>\n    <\/td>\n  <\/tr>\n\n  <tr>\n    <td rowspan='1' class='time'>14:40 &#8211; 15:10<\/td>\n    <td rowspan='1' class='session'>\n      <b>Coffee Break<\/b>\n    <\/td>\n    <td rowspan='1' colspan='2' class='details'><\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='5' class='time'>15:10 &#8211; 16:30<\/td>\n    <td rowspan='5' class='session'>\n      <b>Session: Machine Learning 2<\/b>\n      <br>\n      <small>Chair: Vaughn Betz<\/small>\n    <\/td>\n    <td rowspan='1' class='time'>15:10 &#8211; 15:30<\/td>\n    <td rowspan='1' class='details'>\n      <b>AMA: An Analytical Approach to Maximizing the Efficiency of Deep Learning on Versal AI Engine<\/b>\n      <br>\n      <small>Xiaodong Deng, Shijie Wang, Tianyi Gao, Jing Liu, Longjun Liu and Nanning Zheng<\/small>\n    <\/td>\n  <tr>\n    <td rowspan='1' class='time'>15:30 &#8211; 15:50<\/td>\n    <td rowspan='1' class='details'>\n      <b>A Heterogeneous Acceleration System for Attention-Based Multi-Agent Reinforcement Learning<\/b>\n      <br>\n      <small>Samuel Wiggins, Yuan Meng, Mahesh Iyer and Viktor Prasanna<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>15:50 &#8211; 16:10<\/td>\n    <td rowspan='1' class='details'>\n      <b>Fitop-Trans: Maximizing Transformer Pipeline Efficiency through Fixed-Length Token Pruning on FPGA<\/b>\n      <br>\n      <small>Kejia Shi, Manting Zhang, Keqing Zhao, Xiaoxing Wu, Yang Liu, Jun Yu and Kun Wang<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>16:10 &#8211; 16:20<\/td>\n    <td rowspan='1' class='details'>\n      <b>An Open-Source and Extensible Framework for Fast Prototyping and Benchmarking of Spiking Neural Network Hardware<\/b>\n      <br>\n      <small>Shadi Matinizadeh and Anup Das<\/small>\n    <\/td>\n  <\/tr>\n  <tr>\n    <td rowspan='1' class='time'>16:20 &#8211; 16:30<\/td>\n    <td rowspan='1' class='details'>\n      <b>HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accelerator<\/b>\n      <br>\n      <small>Zhewen Yu, Sudarshan Sreeram, Krish Agrawal, Junyi Wu, Alexander Montgomerie-Corcoran, Cheng Zhang, Jianyi Cheng, Christos-Savvas Bouganis and Yiren Zhao<\/small>\n    <\/td>\n  <\/tr>\n\n  <tr>\n    <td rowspan='1' class='time'>16:30 &#8211; 18:30<\/td>\n    <td rowspan='1' class='session'>\n      <b>Special Session: FPGA Networking<\/b>\n      <br>\n      <small>Organized by Mario Baldi (AMD)<\/small>\n    <\/td>\n    <td rowspan='1' colspan='2' class='details'>\n      <a href=\"http:\/\/asaclab.polito.it\/fpl2024\/networking\/\">Additional Info<\/a>\n    <\/td>\n  <\/tr>\n  \n  <tr>\n      <td rowspan=\"1\" class=\"time\">19:30<\/td>\n      <td rowspan=\"1\" class=\"session\">\n        <b>Social Dinner @ Esperia Restaurant <\/b>\n      <\/td>\n      <td rowspan=\"1\" colspan=\"2\" class=\"details\">   <b> <a href=\"http:\/\/asaclab.polito.it\/fpl2024\/soacial-activity\/#social_dinner\">Social Dinner  <\/a> <\/b> <\/td>\n    <\/tr>\n<\/table>\n\n<\/div>\n\n<div class=\"\"  data-pds-tabs--accordion-initially-open=\"false\" >\n\n<h2>6th September<\/h2>\n<table>\n<tr><th class='time'>TIME<\/th><th class='session'>SESSION<\/th><th class='details' colspan=2>DETAILS<\/th><\/tr>\n<tr><td rowspan='1' class='time'>08:30 &#8211; 09:00<\/td><td rowspan='1' class='session'><b>Registration<\/b> <\/td><td rowspan='1' colspan='2'  class='details'><\/td><\/tr><tr><td rowspan='1' class='time'>09:00 &#8211; 10:00<\/td><td rowspan='1' class='session'><b>Keynote<\/b><br><small>Chair: Lana Josipovic<\/small> <\/td><td rowspan='1' class='time'>09:00 &#8211; 10:00<\/td><td rowspan='1' class='details'><b><a href=\"http:\/\/asaclab.polito.it\/fpl2024\/keynotes\/#keynote_3\">Fantastic Arithmetic Beasts and where to find them<\/a><\/b><\/b><br><small>Florent de Dinechin and Bogdan Pasca<\/small><\/td><\/tr><tr><td rowspan='3' class='time'>10:00 &#8211; 10:40<\/td><td rowspan='3' class='session'><b>Session: Edge &#038; Low-Power Computing<\/b><br><small>Chair: Stefania Perri<\/small> <\/td><td rowspan='1' class='time'>10:00 &#8211; 10:20<\/td><td rowspan='1' class='details'><b>SDA: Low-Bit Stable Diffusion Acceleration on Edge FPGAs<\/b><br><small>Geng Yang, Yanyue Xie, Zhong Jia Xue, Sung-En Chang, Yanyu Li, Peiyan Dong, Jie Lei, Weiying Xie, Yanzhi Wang, Xue Lin and Zhenman Fang<\/small><\/td><tr><td rowspan='1' class='time'>10:20 &#8211; 10:30<\/td><td rowspan='1' class='details'><b>E3HDC: Energy Efficient Encoding for Hyper-Dimensional Computing on Edge Devices<\/b><br><small>Mahboobe Sadeghipourrudsari, Jonas Krautter, Vincent Meyers and Mehdi Tahoori<\/small><\/td><\/tr><tr><td rowspan='1' class='time'>10:30 &#8211; 10:40<\/td><td rowspan='1' class='details'><b>Energy-Aware Synchronization of Hardware Tasks in Virtualized Embedded Systems<\/b><br><small>Cornelia Wulf, G\u00f6khan Akg\u00fcn, Mehdi Safarpour, Anastacia Grishchenko and Diana Goehringer<\/small><\/td><\/tr><\/tr><tr><td rowspan='1' class='time'>10:40 &#8211; 11:10<\/td><td rowspan='1' class='session'><b>Coffee Break<\/b> <\/td><td rowspan='1' colspan='2'  class='details'><\/td><\/tr><tr><td rowspan='4' class='time'>11:10 &#8211; 12:20<\/td><td rowspan='4' class='session'><b>Session: Arithmetic\t\t\t\t<\/b><br><small>Chair: Mario Porrmann<\/small> <\/td><td rowspan='1' class='time'>11:10 &#8211; 11:30<\/td><td rowspan='1' class='details'><b>FPGA Modular Multipliers using Hybrid Reduction Techniques<\/b><br><small>Sergey Gribok, Martin Langhammer and Bogdan Pasca<\/small><\/td><tr><td rowspan='1' class='time'>11:30 &#8211; 11:50<\/td><td rowspan='1' class='details'><b>Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAs<\/b><br><small>Shivam Aggarwal, Hans Jakob Damsgaard, Alessandro Pappalardo, Giuseppe Franco, Thomas B. Preu\u00dfer, Michaela Blott and Tulika Mitra<\/small><\/td><\/tr><tr><td rowspan='1' class='time'>11:50 &#8211; 12:10<\/td><td rowspan='1' class='details'><b>Exploring FPGA designs for MX and beyond<\/b><br><small>Ebby Samson, Naveen Mellempudi, Wayne Luk and George Constantinides<\/small><\/td><\/tr><tr><td rowspan='1' class='time'>12:10 &#8211; 12:20<\/td><td rowspan='1' class='details'><b>Fast and Practical Strassen&#8217;s Matrix Multiplication using FPGAs<\/b><br><small>Afzal Ahmad, Linfeng Du and Wei Zhang<\/small><\/td><\/tr><\/tr><tr><td rowspan='1' class='time'>12:20 &#8211; 13:20<\/td><td rowspan='1' class='session'><b>Lunch<\/b> <\/td><td rowspan='1' colspan='2'  class='details'><\/td><\/tr><tr><td rowspan='5' class='time'>13:20 &#8211; 14:40<\/td><td rowspan='5' class='session'><b>Session: Accelerators<\/b><br><small>Chair: Andrea Guerrieri<\/small> <\/td><td rowspan='1' class='time'>13:20 &#8211; 13:40<\/td><td rowspan='1' class='details'><b>FORC: A High-Throughput Streaming FPGA Accelerator for Optimized Row Columnar File Decoders in Big Data Engines<\/b><br><small>Abdul Wadood, Alec Lu, Ken Zhang and Zhenman Fang<\/small><\/td><tr><td rowspan='1' class='time'>13:40 &#8211; 14:00<\/td><td rowspan='1' class='details'><b>BitBlender: Scalable Bloom Filter Acceleration on FPGAs with Dynamic Scheduling<\/b><br><small>Kenneth Liu, Alec Lu and Zhenman Fang<\/small><\/td><\/tr><tr><td rowspan='1' class='time'>14:00 &#8211; 14:20<\/td><td rowspan='1' class='details'><b>LORA: A Latency-Oriented Recurrent Architecture for GPT Model on Multi-FPGA Platform with Communication Optimization<\/b><br><small>Zhendong Zheng, Qianyu Cheng, Teng Wang, Lei Gong, Xianglan Chen, Cheng Tang, Chao Wang and Xuehai Zhou<\/small><\/td><\/tr><tr><td rowspan='1' class='time'>14:20 &#8211; 14:30<\/td><td rowspan='1' class='details'><b>DTrans: A Dataflow-transformation FPGA Accelerator with Nonlinear-operators fusion aiming for the Generative Model<\/b><br><small>Xuanzheng Wang, Shuo Miao, Peng Qu and Youhui Zhang<\/small><\/td><\/tr><tr><td rowspan='1' class='time'>14:30 &#8211; 14:40<\/td><td rowspan='1' class='details'><b>CFSA: An Efficient CPU-FPGA Synergies Accelerator for Neural Radiation Field Rendering<\/b><br><small>Shangrong Li, Kai Liu, Wei Liu, Zibo Guo and Chongyang Ding<\/small><\/td><\/tr><\/tr><tr><td rowspan='1' class='time'>14:40 &#8211; 14:50<\/td><td rowspan='1' class='session'><b>Closing<\/b> <\/td><td rowspan='1' colspan='2'  class='details'><\/td><\/tr><\/table>\n\n<\/div>\n\n            <\/div>\n        <\/div>\n    <\/div>\n\n\n<p><strong>(*) Michal Servit Best Paper Award Candidates<br>(#) Stamatis Vassiliadis Best Paper Award Candidates<\/strong><\/p>\n\n\n\n<p><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Program (*) Michal Servit Best Paper Award Candidates(#) Stamatis Vassiliadis Best Paper Award Candidates<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"_eb_attr":"","_editorskit_title_hidden":false,"_editorskit_reading_time":0,"_editorskit_is_block_options_detached":false,"_editorskit_block_options_position":"{}","site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"disabled","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-gradient":""}},"footnotes":""},"acf":[],"aioseo_notices":[],"_links":{"self":[{"href":"http:\/\/asaclab.polito.it\/fpl2024\/wp-json\/wp\/v2\/pages\/196"}],"collection":[{"href":"http:\/\/asaclab.polito.it\/fpl2024\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/asaclab.polito.it\/fpl2024\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/asaclab.polito.it\/fpl2024\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/asaclab.polito.it\/fpl2024\/wp-json\/wp\/v2\/comments?post=196"}],"version-history":[{"count":70,"href":"http:\/\/asaclab.polito.it\/fpl2024\/wp-json\/wp\/v2\/pages\/196\/revisions"}],"predecessor-version":[{"id":432,"href":"http:\/\/asaclab.polito.it\/fpl2024\/wp-json\/wp\/v2\/pages\/196\/revisions\/432"}],"wp:attachment":[{"href":"http:\/\/asaclab.polito.it\/fpl2024\/wp-json\/wp\/v2\/media?parent=196"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}